1. Field of the Invention
The present invention relates to a method for fabricating a multilayer microstructure, more particularly to a method for fabricating a multilayer microstructure with balancing residual stress capability.
2. Description of the Related Art
Recently, the fabrication of microelectromechanical systems (MEMS) devices such as pressure sensors, microphones, gas detectors, accelerometers, resonators, micro mirrors and bio-sensors and so on, has developed to exploit mature fabrication processes of semiconductor industry such as the complementary metal oxide semiconductor (CMOS) process. Therefore, the microstructure of a MEMS device may be fabricated together with the integrated circuits of the MEMS device with a single CMOS process to lower the cost. Silicon, polysilicon, interconnects and via layers, etc. commonly used in the CMOS process can be used to form the microstructure of a CMOS-MEMS device.
Then in a post-CMOS process, an etching step is conducted to form a suspended microstructure on the substrate. The etching step may use wet etching or dry etching. The etching rate and the selectivity of the wet etching are better, but the resulted surface tension from the etching solution on the microstructure and the substrate may causes stiction between them. As a result, dry etching is used to avoid stiction. Existing dry etching methods are sputter etching, reactive ion etching (RIE) and plasma etching. Sputter etching uses ion milling to remove the etchant, and is therefore classified as physical etching, which is anisotropic and has low selectivity with respect to the etchant. Plasma etching engages a chemical reaction between the reaction gas and the etchant, and is therefore classified as chemical etching, which is isotropic and has high selectivity with respect to the etchant. Reactive ion etching engages a chemical reaction between the reaction gas and the etchant, and uses ion milling to remove the product of the chemical reaction. It is therefore classified to be between sputter etching and plasma etching, and is anisotropic and has high selectivity with respect to the etchant. The prior art post-CMOS process typically uses RIE in order to form microstructures of high aspect ratio.
FIG. 1a, FIG. 1b and FIG. 1c are the cross-sectional diagrams illustrating the flow of a prior art fabrication method for a CMOS-MEMS device 100. Through the CMOS process, a CMOS circuit 120 and a multilayer structure 130 are formed in a substrate 110 as shown in FIG. 1a. The multilayer structure 130 includes inter-stacked dielectric layers 111 and patterned metal layers 131. The patterned metal layers 131 are aligned to form etching through holes 132. The metal layers 131 are formed with Metal 1, Metal 2, Metal 3 and Metal 4, which are originally used as interconnects. The material of the substrate 110 and the dielectric layers 111 respectively includes silicon and silicon dioxide, primarily. In the post-CMOS process as illustrated in FIG. 1b, the dielectric layers 111 is etched by using anisotropic RIE until the substrate 110 is exposed, wherein the metal layer 131 is used as the mask for anisotropic RIE, and trifluoromethane and oxygen are used as reaction gases for anisotropic RIE. Next, as illustrated in FIG. 1c, the substrate 110 is etched by using isotropic RIE in order to form a suspended multilayer microstructure 130′, wherein sulfur hexafluoride (SF6) and oxygen are used as reaction gases for isotropic RIE.
Referring to FIG. 1c, since the coefficient of thermal expansion of the metal layers 131 and the dielectric layer 111 interposed between every two of the metal layers 131 are different, residual stress may be resulted between any of the metal layers 131 and its adjacent dielectric layer 111. When a dielectric layer exists between symmetrical upper and lower metal layers, the residual stress between the upper metal layer and the dielectric layer, and between the lower metal layer and the dielectric layer can cancel each other out; otherwise, the residual stress is not balanced and may deform the structure. The bottom-most dielectric layer 111, is covered by the metal layers 131 as illustrated in FIG. 1c, and is not able to be removed by anisotropic RIE, and therefore, the suspended multilayer microstructure 130′ formed on the substrate 110 is not symmetrical, which results in the residual stress causing severe curl-up of the microstructure as shown in FIG. 2. Such deformation affects not only the mechanical property of the MEMS device, but also its electrical properties.
In order to solve aforementioned problems, the present invention discloses a method for fabricating a multilayer microstructure with balancing residual stress capability so that the residual stress is balanced and the flatness of the MEMS device is maintained.